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W83194R-81
100MHZ CLOCK FOR SIS CHIPSET 1.0 GENERAL DESCRIPTION
The W83194R-81 is a Clock Synthesizer for SiS chipset. W83194R-81 provides all clocks required for high-speed RISC or CISC microprocessor such as AMD,Cyrix,Intel Pentium and also provides 16 different frequencies of CPU clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194R-81 makes SDRAM in synchronous or asynchronous frequency with CPU clocks. The W83194R-81 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and W83194R-81 provides the 0.25%, 0.5% center type spread spectrum to reduce EMI. The W83194R-81 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50O 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
* * * * * Supports PentiumTM, PentiumTM Pro, AMD and Cyrix CPUs with I2C. 3 CPU clocks 13 SDRAM clocks for 3 DIMMs 6 PCI synchronous clocks. Optional single or mixed supply: (Vdd = Vddq4=Vddq3 = Vddq2b = 3.3V, Vddq2=2.5V) or (Vdd = Vddq4=Vddq3 = 3.3V, Vddq2=Vdq2b = 2.5V) Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns SDRAM frequency synchronous or asynchronous to CPU clocks Smooth frequency switch with selections from 66 to 133mhz(including 90MHz) I2C 2-Wire serial interface and I2C read back 0.25%, 0.5% center type spread spectrum to reduce EMI Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) MODE pin for power Management 48 MHz for USB 24 MHz for super I/O 48-pin SSOP package
* * * * * * * * * *
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY 3.0 BLOCK DIAGRAM
PLL2
SEL24_14# Xin Xout 48MHz
O2
SIO
XTAL OSC PLL1
Spread Spectrum
3
REF(0:2) IOAPIC
STOP
CPU_STOP# 3
CPUCLK(0:2)
*FS(0:2) 3 *MODE CPU3.3_2.5# *SD_SEL#
LATCH
5
13 PCI clock Divder
SDRAM(0:12)
POR
SDRAM_STOP# CPU_STOP# PCI_STOP# PD# *SDAT A*SCLK
STOP
5
PCICLK(0:4) PCICLK_F
Contro l Logic Config . Reg.
PCI_STOP#
4.0 PIN CONFIGURATION
Vdd REF0/ *MODE Vss Xin Xout Vddq4 PCICLK_F/ *FS1 PCICLK0/ *FS2 Vss PCICLK1 PCICLK2 PCICLK3 PCICLK4 Vddq4 SDRAM12 Vss *CPU_STOP#/SDRAM11 *PCI_STOP#/SDRAM10 Vddq3 *SDRAM_STOP#/SDRAM 9 *PD#/SDRAM 8 Vss *SDATA *SDCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vddq2 IOAPIC REF1/ *SD_SEL# Vss REF2/CPU3.3_2.5# CPUCLK0 Vddq2b CPUCLK1 CPUCLK 2 Vss SDRAM 0 SDRAM 1 Vddq3 SDRAM 2 SDRAM 3 Vss SDRAM 4 SDRAM 5 Vddq3 SDRAM 6 SDRAM 7 Vss 48MHz/*FS0 SIO/*SEL24_14#
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY 5.0 PIN DESCRIPTION
IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250k pull-up
5.1 Crystal I/O
SYMBOL Xin Xout PIN 4 5 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally.
5.2 CPU, SDRAM, PCI Clock Outputs
SYMBOL CPUCLK [ 0:2 ] PIN 40,41,43 I/O OUT FUNCTION Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. Vddq2b is the supply voltage for these outputs. If MODE =1 (default), then this pin is a SDRAM clock buffered output of the crystal. If MODE = 0 , then this pin is CPU_STOP# input used in power management mode for synchronously stopping the all CPU clocks. If MODE = 1 (default), then this pin is a SDRAM clock output. If MODE = 0 , then this pin is PCI_STOP # and used in power management mode for synchronously stopping the all PCI clocks. If MODE = 1 (default), then this pin is a SDRAM clock output. If MODE = 0 , then this pin is SDRAM_STOP # and used in power management mode for stopping the all SDRAM clocks. If MODE = 1 (default), then this pin is a SDRAM clock output. If MODE = 0 , then this pin is PD # and used to power down the device into a power down state. SDRAM clock outputs which have the same frequency as CPU clocks. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Free running PCI clock during normal operation.
SDRAM11/ *CPU_STOP#
17
I/O
SDRAM10/ *PCI_STOP#
18
I/O
SDRAM9/ *SDRAM_STOP#
20
I/O
SDRAM8/ *PD#
21
I/O
SDRAM[0:7], SDRAM12 PCICLK_F/ *FS1
28,29,31,32,34 , 35,37,38,15 7
O I/O
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY
5.2 CPU, SDRAM, PCI Clock Outputs, continued
SYMBOL PCICLK 0 / *FS2
PIN 8
I/O I/O
FUNCTION Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. PCI clock during normal operation. Low skew (< 250ps) PCI clock outputs.
PCICLK [ 1:4 ]
10,11,12,13
OUT
5.3 I2C Control Interface
SYMBOL *SDATA *SDCLK PIN 23 24 I/O I/O IN
2
FUNCTION Serial data of I C 2-wire control interface Serial clock of I2C 2-wire control interface
5.4 Fixed Frequency Outputs
SYMBOL IOAPIC REF0 / *MODE PIN 47 2 I/O O I/O FUNCTION 2.5V fixed 14.318MHz 3.3V, 14.318MHz reference clock output. Internal 250k pull-up. Function select pin. 3.3V, 14.318MHz reference clock output Internal 250k pull-up. Latched input at Power On selects the frequencies for clock outputs. Internal 250k pull-up. Latched input for CPU3.3#_2.5 at initial power up. Reference clock during normal operation. Latched high - Vddq2b = 2.5V Latched low - Vddq2b = 3.3V *SEL24_14# controls the frequency of SIO. If logic 0 at power on, SIO=14.318. If logic 1, SIO=24MHz for super I/O. Internal 250k pull-up. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 48MHz output for USB during normal operation.
REF1 /*SD_SEL#
46
I/O
REF2 / CPU3.3#_2.5
44
I/O
SIO / *SEL24_14#
25
I/O
48MHz / *FS0
26
I/O
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY
5.5 Power Pins
SYMBOL Vdd Vddq2 Vddq2b Vddq3 Vddq4 Vss PIN 1 48 42 19, 30, 36 6,14 3,9,16,22,27, 33,39,45 FUNCTION Power supply for REF0 crystal and core logic. Power supply for REF1,IOAPIC output, 2.5V. Power supply for REF2, CPUCLK[0:2], either 2.5V or 3.3V. Power supply for SDRAM and 48/24MHz outputs. Power supply for PCICLK outputs. Circuit Ground.
6.0 FREQUENCY SELECTION BY HARDWARE
SD_SEL FS2 FS1
FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CPU
(MHz)
SDRAM
(MHz)
PCI (MHz) 33.35 30 31.7 33.4 30 37.3 31 33.3 33.4 30 33.32 31.7 33.4 37.3 31 33.3
REF (MHz) IOAPIC 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
66.70 90 95.25 100.2 100 112 124 133.3 66.8 75 83.3 95.25 100.2 112 124 133.3
100.05 90 63.4 66.8 75 74.7 82.7 88.9 66.8 75 83.3 95.25 100.2 112 124 133.3
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY
7.0 CPU 3.3#_2.5 BUFFER SELECTION
CPU 3.3#_2.5 ( Pin 44 ) Input Level 1 0 CPU Operate at VDD = 2.5V VDD = 3.3V
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY 8.0 FUNTION DESCRIPTION
8.1 POWER MANAGEMENT FUNCTIONS
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up, external circuitry should allow 3 ms for the VCO to stabilize prior to enabling clock outputs to assure correct pulse widths. When MODE=0, pins 17, 18, 20 and 21 are inputs (PCI_STOP#), (CPU_STOP#), (SDRAM_STOP#), (PD#). when MODE=1, these functions are not available. A particular clock could be enabled as both the 2-wire serial control interface and one of these pins indicate that it should be enabled. The W83194R-81 may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop. The CPU and PCI clocks transform between running and stop by waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after which high levels of the output are either enabled or disabled.
MODE PIN-POWER MANAGEMENT INPUT
MODE(Pin2) 0 (Input) 1 (Output) Pin17 CPU_STOP# SDRAM11 Pin18 PCI_STOP# SDRAM10 Pin20 SDRAM_STOP# SDRAM9 Pin21 PD# SDRAM8
PD#
CPU_STOP#
PCI_STOP#
SDRAM _STOP#
PCI [0:4]
SDRAM [0:12]
CPU[1:2]
XTAL & VCOs
0 1 1 1 1 1 1 1 1 1
X X 1 1 1 1 0 0 0 0
X X 1 1 0 0 1 1 0 0
X X 1 0 1 0 1 0 1 0
Low Running Running Running Low Low Running Running Low Low
Low Running Running Running Running Low Running Low Running Low
Low Running Running Running Running Running Low Low Low Low
Low Running Running Running Running Running Running Running Running Running
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY
8.2 2-WIRE I2C CONTROL INTERFACE
The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83194R-81 initializes with default register settings, and then it optional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a start condition followed by 7-bit slave address [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: Bytes sequence order for I2C controller :
Clock Address A(6:0) & R/W
Ack
8 bits dummy Command code
Ack
8 bits dummy Byte count
Ack
Byte0,1,2... until Stop
Set R/W to 1 when read back the data sequence is as follows, [1101 0011] :
Clock Address A(6:0) & R/W
Ack
Byte 0
Ack
Byte 1
Ack
Byte2, 3, 4... until Stop
8.3 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged.
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY 8.3.1 Register 0: CPU Frequency Select Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description 0 = O0.25% Spread Spectrum Modulation 1 = O0.5% Spread Spectrum Modulation SSEL2 ( Frequency table selection by software via I2C) 2 SSEL1 ( Frequency table selection by software via I C) SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit 6:4 and Bit2 SSEL3 (Frequency table selection by software via I2C ) 0 = Normal 1 = Spread Spectrum enabled 0 = Running 1 = Tristate all outputs
Frequency table selection by software via I2C
SSEL3 SSEL2 SSEL1
SSEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CPU
(MHz)
SDRAM
(MHz)
PCI (MHz) 33.35 30 31.7 33.4 30 37.3 31 33.3 33.4 30 33.32 31.7 33.4 37.3 31 33.3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
66.70 90 95.25 100.2 100 112 124 133.3 66.8 75 83.3 95.25 100.2 112 124 133.3
100.05 90 63.4 66.8 75 74.7 82.7 88.9 66.8 75 83.3 95.25 100.2 112 124 133.3
REF (MHz) IOAPIC 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY
8.3.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 Pin 40 41 43 Reserved Reserved Reserved Reserved CPUCLK2 (Active / Inactive) CPUCLK1 (Active / Inactive) CPUCLK0 (Active / Inactive) Latched FS0# Description
8.3.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 Pin 7 13 12 11 10 8 Latched FS1# PCICLK_F (Active / Inactive) Reserved PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK0 (Active / Inactive) Description
8.3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 28 29 31 32 34 35 37 38 SDRAM7 (Active / Inactive) SDRAM6 (Active / Inactive) SDRAM5 (Active / Inactive) SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive) Description
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY 8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 25 26 15 17 18 20 21 Reserved 24/14MHz(Active / Inactive) 48MHz(Active / Inactive) SDRAM12 (Active / Inactive) SDRAM11 (Active / Inactive) SDRAM10 (Active / Inactive) SDRAM9 (Active / Inactive) SDRAM8 (Active / Inactive) Description
8.3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 Pin 47 44 46 2 Reserved Latched FS2# Reserved IOAPIC (Active / Inactive) Latched SD_SEL REF2 (Active / Inactive) REF1 (Active / Inactive) REF0 (Active / Inactive) Description
8.3.7 Register 6: Winbond Chip ID Register (Read Only)
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 0 1 0 1 0 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Description
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY 9.0 SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Vdd , VIN TSTG TB TA Parameter Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature Rating - 0.5 V to + 7.0 V - 65C to + 150C - 55C to + 125C 0C to + 70C
9.2 AC CHARACTERISTICS
Vddq4 = Vdd = Vddq3 = 3.3V 5 %, Vddq2=Vddq2b = 2.375V~2.9V , TA = 0C to +70C Parameter Output Duty Cycle CPU/SDRAM to PCI Offset Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM) CPU/SDRAM Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) & Fall (2.0V ~0.4V) Time Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion VRBE 2.1 V tTLH tTHL Vover 1.5 V 0.4 1.6 ns 15 pF Load on CPU and PCI outputs 22 at source of 8 inch PCB run to 15 pF load Ring Back must not enter this range. BWJ 500 KHz tJA 500 ps tOFF tSKEW tCCJ Symbol Min 45 1 Typ 50 Max 55 4 250 O250 Units % ns ps ps Test Conditions Measured at 1.5V 15 pF Load Measured at 1.5V 15 pF Load Measured at 1.5V
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY
9.3 DC CHARACTERISTICS
Vddq4 = Vdd = Vddq3 = 3.3V 5 %, Vddq2=Vddq2b = 2.375V~2.9V , TA = 0C to +70C Parameter Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 4 mA Output High Voltage IOH = 4mA Tri-State leakage Current Dynamic Supply Current for Vdd + Vddq3 Dynamic Supply Current for Vddq2 + Vddq2b CPU Stop Current for Vdd + Vddq3 CPU Stop Current for Vddq2 + Vddq2b PCI Stop Current for Vdd + Vddq3 IPD3 mA ICPUS2 mA Same as above ICPUS3 mA Same as above Idd2 mA Ioz Idd3 10 A mA CPU = 66.6 MHz PCI = 33.3 Mhz with load Same as above VOH 2.4 Vdc All outputs using 3.3V power Symbol VIL VIH IIL IIH VOL 2.0 -66 5 0.4 Min Typ Max 0.8 Units Vdc Vdc A A Vdc All outputs Test Conditions
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY 9.4 BUFFER CHARACTERISTICS 9.4.1 TYPE 1 BUFFER FOR CPU (0:2)
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.4 1.6 27 Min -27 -27 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 2.0V Vout = 1.2 V Vout = 0.3 V 10 pF Load 20 pF Load
9.4.2 TYPE 2 BUFFER FOR IOAPIC
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.7 V and 1.7 V Rise/Fall Time Max Between 0.7 V and 1.7 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.4 1.8 28 -29 Min Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.4 V Vout = 2.7V Vout = 1.0 V Vout = 0.2 V 10 pF Load 20 pF Load
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY 9.4.3 TYPE 3 BUFFER FOR REF(0:2), 24MHZ, 48MHZ
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 1.0 4.0 29 Min -29 -23 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 3.135V Vout = 1.95 V Vout = 0.4 V 10 pF Load 20 pF Load
9.4.4 TYPE 4 BUFFER FOR SDRAM(0:12)
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.5 1.3 53 -46 Min Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.65V Vout = 3.135V Vout = 1.65 V Vout = 0.4 V 20 pF Load 30 pF Load
9.4.5 TYPE 5 BUFFER FOR PCICLK(0:4, F)
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.5 2.0 30 38 Min -33 -33 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 3.135 V Vout = 1.95 V Vout = 0.4 V 15 pF Load 30 pF Load
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY 10.0 POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram
CPUCLK (Internal) PCICLK (Internal) PCICLK_F CPU_STOP# 1 2 1 2
CPUCLK[0:3]
SDRAM
For synchronous Chipset, CPU_STOP# pin is a synchronous "active low "i nput pin used to stop the CPU clocks for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume output with full pulse width. In this case, CPU locks on latency" is less than 2 CPU clocks and locks off latency is less then 2 CPU clocks.
10.2 PCI_STOP# Timing Diagram
CPUCLK (Internal) PCICLK (Internal) PCICLK_F PCI_STOP# 1 2 1 2
PCICLK[0:4]
For synchronous Chipset, PCI_STOP# pin is a synchronous ctive low" input pin used to stop the PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output with full pulse width. In this case, PCI locks on latency" is less than 1 PCI clocks and locks off latency is less then 1 PCI clocks.
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY 11.0 ORDERING INFORMATION
Part Number W83194R-81 Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C
12.0 HOW TO READ THE TOP MARKING
W83194R-81 28051234 814GBB
1st line: Winbond logo and the type number: W83194R-81 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR BB: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: Dec. 1998 Revision 0.20
W83194R-81
PRELIMINARY 13.0 PACKAGE DRAWING AND DIMENSIONS
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
Publication Release Date: Dec. 1998 Revision 0.20
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